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Issue #372
Feature request - add syntax highlighting to C pre-processor directives
| Status: | Feature | Start date: | 08/03/2011 | |
|---|---|---|---|---|
| Priority: | Low | Due date: | ||
| Assignee: | Michael McNamara | % Done: | 0% |
|
| Category: | Indents | |||
| Target version: | - | Estimated time: | 1.00 hour |
Description
Can you add left-justified indendation and highlighting for C pre-processor directives (#ifdef, etc.) with the same formatting as the verilog pre-processor directives (`ifdef, etc.).
This automatic highlighting will assist in maintain proper formatting for verilog files leveraging more advance pre-processing before handing off to simulation/synthesis tools.
History
Updated by Wilson Snyder almost 2 years ago
My first inclination would be to reject this, since I've only seen one other company doing it, and that was well before the SystemVerilog preprocessor features, and also since the syntax highlighting is complicated enough as is ("# ifdef" is a delay of a variable ifdef, and perfectly legal).
But, I'd be inclined to hear Mac's opinion.
Updated by Wilson Snyder over 1 year ago
- Status changed from New to Feature
- Priority changed from Normal to Low
From Mac:
Yeah. Disambiguating #ifdef from a delay in our pattern matching processor will have a impact on speed; and as you say such usage of cpp instead of the built in preprocessor for Verilog is not common.
I did support vpp for a while, which implements the balance of the preprocessor features that are in cpp but not Verilog, implementing these as `elif instead of #elif and the like. I will dust that off some day soon....
I will mark it as low priority.
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