Verilog-mode

reg [31:0] sum;
reg [31:0] a;
reg [31:0] b;

always@(posedge clk or negedge rst) begin
   if (!rst) begin
      /*AUTORESET*/
      // Beginning of autoreset for uninitialized flops
      sum <= 32'h0;
      tmp <= 33'h0;
      // End of automatics
   end
   else begin
      reg [32:0] tmp;
      tmp = a + b;
      if (tmp[32])
        sum <= 32'hffffffff;
      else
        sum <= tmp[31:0];
   end
end

Obviously, the code above does not compile because the variable 'tmp' is out of scope within the reset block.