AUTORESET adds resets for variables that are out of scope
|Assignee:||Wilson Snyder||% Done:||
reg [31:0] sum; reg [31:0] a; reg [31:0] b; always@(posedge clk or negedge rst) begin if (!rst) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops sum <= 32'h0; tmp <= 33'h0; // End of automatics end else begin reg [32:0] tmp; tmp = a + b; if (tmp) sum <= 32'hffffffff; else sum <= tmp[31:0]; end end
Obviously, the code above does not compile because the variable 'tmp' is out of scope within the reset block.
Updated by Wilson Snyder almost 2 years ago
- Category set to Autos
- Status changed from New to Assigned
- Assignee set to Wilson Snyder
Agreed. I'll look at a fix, it won't be this week because it's not simple; the parser for autoreset doesn't know how to handle declarations.
Updated by Wilson Snyder over 1 year ago
- Status changed from Assigned to Closed
It was too difficult to parse temporaries, so instead with `verilog-auto-reset-blocking-in-non' set (perhaps as a Local Variable - see the docs) it will not reset any signals assigned with = in a block with <= assignments.
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