Verilator

I have a module that looks like this:

module moda(inout wire [4:0] d);
endmodule

It works fine if I instantiate it like this:

module top;
    wire [4:0] d;

    moda a0(.d(d[4:0]));
endmodule

but fails with "Unsupported: Tristate pin not connected to simple net" if I try to connect it to a slice of a wider bus like this:

module top;
    wire [9:0] d;

    moda a0(.d(d[4:0]));
endmodule

It seems like d is a simple net in both cases.