Verilog-Perl

Sure. I can give it a shot if you give me a sense of what's required and where to update things.

Cool!

See ADDING A NEW FEATURE in internals.pod in the kit. Basically you'll need to make a test. Then add $past as yD_PAST in verilog.l, .y. Add $past as a new statement to verilog.y (taking a number and event_control - you can see VParse.y in the Verilog-Perl kit) and make it generate an AstPast node. Define AstPast in AstNodes.h. You should now be able to compile and run the test, but it will get runtime errors later on as Verilator doesn't know what to do with the AstPast.

So in V3Assert.cpp add a visit(AstPast*) function. At some point this will do a complicated FSM, for now it can just make N temporary variables (where N is the number of cycles of $past). The AstPast is replaced (replaceNode) with an AstVarRef(temp-variable-n). Then in the module (under m_modp) adds an AstAlways(sentree-from-past, AstAssign(temp-variable-n, varref-from-past)). This will make a lot more sense as you follow along with the code!

In short, it's converting it to this

module test;
reg clk, rst, signal_a;
reg Vpast_rst_10;
assert property (@(posedge clk)
          disable iff (rst
//            || $past (rst,1,,@(posedge clk)
              || Vpast_rst_10    // 10 is an arbitrary incrementing number
              )) "assert 0" );
always @ (posedge clk)
    Vpast_rst_10 <= rst;

Note this technique will work with any $past even on different clocks, anywhere in the assert.

If you have a lot of these (hundreds) you can get slightly fancier and more efficient by making a hash so that you reuse created Vpast_... always statements when in multiple assertions the $past expression is identical.

If you get only part way, that's still helpful, feel free to ask questions.

bison is crapping out. Ideas?

bison -t -d -k -v -p VParseBison -b VParseBison_pretmp -o VParseBison_pretmp.c VParseBison_pretmp.y

bison here is version 1.857c. From the version check it seems like that should be OK, yeah?

Program received signal SIGABRT, Aborted.
0x0000002a9569a26d in raise () from /lib64/tls/libc.so.6
(gdb) where
#0  0x0000002a9569a26d in raise () from /lib64/tls/libc.so.6
#1  0x0000002a9569ba6e in abort () from /lib64/tls/libc.so.6
#2  0x00000000004066fa in warn ()
#3  0x00000000004069c3 in warn ()
#4  0x0000002a9568840b in __libc_start_main () from /lib64/tls/libc.so.6
#5  0x0000000000401a7a in ?? ()
...

Sorry, I wasn't paying attention above, I thought this was a Verilator bug, not Verilog-Perl. Verilog-Perl is supposed to handle all asserts, but the same general process applies; put a test case into verilog/parser_sv09.v then edit the bison file. You seem to have translated my mis-direction well ;)

Anyhow, as to the crash can you send your diffs?

I should have mentioned -- that crash occurs on Git HEAD with no modifications.

I'm wondering if I just have a bad bison install as this doesn't seem Verilog-Perl related. I'm going to compile a local bison to see if that helps.

That does seem strange. Yes, I'd try a new bison.

Sigh. bison-2.5 doesn't crash, but fails with "Broken pipe".

What version do you use? I'll try to match that.

Does it work when you run the command standalone?

I have an outstanding tester bug I wouldn't mind releasing, if this is getting too painful I'll just make the change and push a new kit for you. (The size of the edit for Verilog Perl vs. Verilator is quite smaller.)

I'm on 2.3. I've run 2.5 too, so that should be fine.

I've been running the command standalone just to remove any doubt of where the issue is. I really don't mind getting my hands in the code, but this is a bit of a non-starter for me. If you want to make the change, go for it. Otherwise, I'll try to find a different dev box with a working bison environment.

You're awesome, man. Thanks!