Verilator

Hi,

I recently verilated our own Network-on-Chip implementation. For interaction between the system and the uut pins I created a transactor for SystemC TLM. The problem, that came up, is that the interface has valid and ready signals. Their width is determined by the number of virtual channels which is a parameter to the module. Apparently I now have different module interfaces, namely a Mesh_v1 and Mesh_v2 version for one and two channels respectively. The interface ports are then of type bool and vluint32_t. As the transactor should be used with each version, I came up with the idea to force certain ports to be of type sc_bv<V>. This also makes life easier in the transactor itself. As the command line switches did not provide the required behavior (I want to keep other signals as vluint64_t), I created a simple patch, that you can please find attached.

Please comment on the patch, whether it makes sense in your opinion and how it may be improved.

Thanks in advance!

Bye, Stefan