Instantiate per bit array of modules with sub-range as output #414
Labels
resolution: fixed
Closed; fixed
type: feature-IEEE
Request to add new feature, described in IEEE 1800
Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 414 from https://www.veripool.org
Original Date: 2011-11-04
Original Assignee: Wilson Snyder (@wsnyder)
Verilator does not like per bit array instantiations of modules where the output wire is not the full declared size of the wire. For example:
The error message " Unsupported: Per-bit array instantiations with output connections to non-wires." suggests Verilator has become confused. The following works just fine:
as does
The key seems to be using the full declared width of the output wire.
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