Verilator

Verilator does not like per bit array instantiations of modules where the output wire is not the full declared size of the wire. For example:

   wire [17:10] bitout;
   wire [27:24] short_bitout;
   wire [7:0]     allbits;
   wire [15:0]     twobits;

   sub
     i_sub3 [7:4] (.allbits (allbits),
           .twobits (twobits[15:8]),
           .bitout (bitout[17:14]));

The error message " Unsupported: Per-bit array instantiations with output connections to non-wires." suggests Verilator has become confused. The following works just fine:

   sub
     i_sub4 [7:4] (.allbits (allbits),
           .twobits (twobits[15:8]),
           .bitout (short_bitout[27:24]));

as does

   sub
     i_sub5 [7:0] (.allbits (allbits),
           .twobits (twobits),
           .bitout (bitout[17:10]));

The key seems to be using the full declared width of the output wire.