Verilator

Test case:

typedef logic [7-1:0] wb_ind_t;
typedef logic [7-1:0] id_t;

module test ( output wb_ind_t out,
              input id_t in );

   function wb_ind_t line_wb_ind( id_t id );
      if( id[$bits(id_t)-1] == 0 )
        return {2'b00, id[$bits(wb_ind_t)-3:0]};
      else
        return {2'b01, id[$bits(wb_ind_t)-3:0]};
   endfunction // line_wb_ind

   assign out = line_wb_ind( in );

endmodule // test

Generated code:

void Vtest::_combo__TOP__2(Vtest__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_PRINTF("    Vtest::_combo__TOP__2\n"); );
    Vtest* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Body
    VL_ASSIGN_ISI(7,vlTOPp->__Vcellinp__v__in, vlTOPp->in);
    // ALWAYS at test.v:14
    vlTOPp->__Vfunc_v__DOT__line_wb_ind__0__id = vlTOPp->__Vcellinp__v__in;
    {
    {
        if ((0 == (1 & ((IData)(vlTOPp->__Vfunc_v__DOT__line_wb_ind__0__id) 
                >> 6)))) {
        vlTOPp->__Vfunc_v__DOT__line_wb_ind__0__Vfuncout 
            = (0x1f & (IData)(vlTOPp->__Vfunc_v__DOT__line_wb_ind__0__id));
        goto __Vlabel2;
        } else {
        goto __Vlabel1;
        vlTOPp->__Vfunc_v__DOT__line_wb_ind__0__Vfuncout 
            = (0x20 | (0x1f & (IData)(vlTOPp->__Vfunc_v__DOT__line_wb_ind__0__id)));
        }
    }
    __Vlabel2: ;
    }
    __Vlabel1: ;
    vlTOPp->__Vcellinp__v__out = vlTOPp->__Vfunc_v__DOT__line_wb_ind__0__Vfuncout;
}

else part is never executed because of goto in front of assignment.