Issue #422: Verilog::Parser empty generate endgenerate - Verilog-Perl - Veripool

Issue #422

Status:

Closed

Start date:

11/28/2011

Priority:

Low

Due date:

Assignee:

% Done:

Category:

Target version:

Description

Below code would generate error:

%Error: walo_001.v:8: syntax error, unexpected endgenerate

@ module any ( // input a, // output b, ); // always @(*) begin // end endgenerate

generate
endgenerate

generate

endmodule @

regards, Walo

Simple enough, thanks for the report.

In git towards 3.313.

In 3.313.

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