Verilator

First off, great tool! We are looking forward to putting this to use in conjunction with our SystemC testbench.

We have a design which uses Verilog arrays extensively, and while the wire and reg forms seem to work just fine, our array parameters cause Verilator to issue unexplained warnings and also crash. Here's a sample bit of code:

module testing ();

    parameter [0:3][3:0] FOO = { 4'h0, 4'h1, 4'hE, 4'hF };

    parameter BAR = FOO[3];

endmodule

When we process that example with Verilator (by calling verilator -sc testing.v) the result is:

%Warning-WIDTH: testing.v:3: Operator VAR 'FOO' expects 4 bits on the Initial value, but Initial value's CONCAT generates 16 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: testing.v:5: Internal: Unexpected Call
%Error: Internal Error: testing.v:5: ../V3AstNodes.h:453: Unexpected Call
%Error: Command Failed verilator_bin -sc testing.v

As far as we can tell, this warning is invalid. It appears that the array assignment isn't being handled correctly, and then the subsequent array access leads to an internal error (which is identical in nature to bug393).