Verilog-mode

I've just switched to using Verilog Mode v736 (in GNU emacs 23.1.1), and I've noticed that indentation and auto-commenting seem to behave very strangely in the second always @(*) block in a file. Here's a simple example (also attached as a file)

module example;

   always @(*)
      begin
         // some statements
         a = 0;

         // enough blank lines to get the end to be auto-commented...

      end // always @ (*)

   always @(*)
   begin // <-- this begin not indented

      // some more logic

      b = 0;

      // more blank lines, but no auto-comment appears on the end below

   end

The above is how the code looks after it has been typed in. Note the two odd things:

(1) the second "begin" is not indented under the always @(*) like the first one. Pressing TAB on that line makes no difference.

(2) the second "end" does not get auto-commented.

But things get even stranger if I then do C-c C-r to redo the auto-generated comments. Then it looks like this:

module example;

   always @(*)
      begin
         // some statements
         a = 0;

         // enough blank lines to get the end to be auto-commented...

      end // always @ always

   always @(*)
   begin // <-- this begin not indented

      // some more logic

      b = 0;

      // more blank lines, but no auto-comment appears on the end below

   end // always @ begin

Now, both "end" lines get auto-commented, but the "always (*)" has turned into "always " - the "@(*)" is now missing, despite having been there in the first example. Even more weird, if I now put the cursor on the line where the second "begin" is and hit TAB, it gets aligned way out right:

   always @(*)
             begin // <-- this begin not indented

I suspect there might be one underlying bug here, causing both issues? Note that these issues do not occur if I use the alternative "always @*" syntax, i.e. without the parentheses.

Best regards, Alan