Verilog-mode

I have noticed this incorrect indentation of code lines that are generated by AUTORESET, if they are subsequently re-indented after AUTORESET creates them. Here is an example code fragment:

module ar_misalign;

   parameter SBW = 19;

   reg [2:0]            f_state;
   reg [(SBW-1):0]      tag_read;
   reg                  flush_ip;
   reg                  fetch_go;
   reg                  fetch_tag_rd_req;
   reg                  ti_mb_ready;

   always @(posedge clk or negedge rst_n)
      if (!rst_n) begin
         /*AUTORESET*/
         // Beginning of autoreset for uninitialized flops
         f_state <= 3'h0;
         fetch_go <= 1'h0;
         fetch_tag_rd_req <= 1'h0;
         flush_ip <= 1'h0;
         tag_read <= {(1+((SBW-1))){1'b0}};
ti_mb_ready <= 1'h0;
// End of automatics
end
      else begin
         // dummy code for example
         f_state <= 3'h3;
         fetch_go <= 1'h1;
         fetch_tag_rd_req <= 1'h1;
         flush_ip <= 1'h1;
         tag_read <= 14;
         ti_mb_ready <= 1'h1;
      end

endmodule // ar_misalign

You see that the last three lines of the reset assignments are not indented at all. AUTORESET generated them correctly, but they become incorrect if re-indented, either individually by hitting TAB on those lines, or by using C-M-\ to re-indent a region.