Verilog-mode

The indentation of an expression continued over multiple lines is incorrect when the first line of the expression ends with ']'. For example, see the indentation of the ':' of the conditional operator in the two separate instances in the following code. In the first instance, the first line of the continued expression ends with 'ctl_in', and the following indentation is fine. In the second instance, the first line of the continued expression ends with 'data_in[63:0]', and the following indentation is broken.

// emacs-versions: both GNU Emacs 21.4.1
//                 and  GNU Emacs 23.1.1
// verilog-mode-version: 774

module foo
  (input [63:0]     data_in,
   input         ctl_in,

   output [63:0]    data_out,
   output           ctl_out);

   // good: electric-verilog-tab nicely aligns continued expression
   assign ctl_out = data_in[0] ? ctl_in
            :            1'h0;

   // bad: electric-verilog-tab does not align continued expression
   //      if first line ends with ']'
   assign data_out = data_in[1] ? data_in[63:0]
     :            64'h0;

endmodule