Verilator

Test case:

`define CSR_LOCAL_ADDR_WIDTH  12
`define CSR_SUBMOD_SEL_NUM_BITS `CSR_LOCAL_ADDR_WIDTH-`CSR_SUBMOD_SEL_NUM_BITS +: `CSR_SUBMOD_SEL_NUM_BITS
`define CSR_SUBMOD_SEL_BITS     `CSR_LOCAL_ADDR_WIDTH-`CSR_SUBMOD_SEL_NUM_BITS +: `CSR_SUBMOD_SEL_NUM_BITS
`define CSR_SUBMOD_ADDR_BITS    0 +: `CSR_LOCAL_ADDR_WIDTH-`CSR_SUBMOD_SEL_NUM_BITS

typedef   logic [`CSR_LOCAL_ADDR_WIDTH-1:0]  csr_laddr_t;
typedef   logic [64-1:0]                     csr_data_t;

module mod_a
  (
   output csr_data_t                 csr_rdata_out,

   input logic                       csr_en_in,
   input logic                       csr_we_in,
   input csr_laddr_t                 csr_addr_in,
   input csr_data_t                  csr_wdata_in,
   );

endmodule

module mod_b
  (
   output csr_data_t                 csr_rdata_out,

   input logic                       csr_en_in,
   input logic                       csr_we_in,
   input csr_laddr_t                 csr_addr_in,
   input csr_data_t                  csr_wdata_in,
   );

   mod_a u_mod_a(.csr_en_in  (csr_en_in && (csr_addr_in[`CSR_SUBMOD_SEL_BITS] == 7)),
                 .csr_addr_in(csr_laddr_t'(csr_addr_in[`CSR_SUBMOD_ADDR_BITS])),
                 .* );

endmodule // mod_b

verilator never exits.