Verilator

Hi,

Attached is a test for packed arrays. The test is based on the verilator test environment (except for the checksum) and can be run with "test_regress/t/t_array_packed.pl". It compiles and runs properly on ncsim (the -nc) option. Here is the list of issues:

1. expression LHS size is not calculated correctly, note that in all expressions both sizes have the same bitsize %Warning-WIDTH: t/t_array_packed.v:46: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS's REPLICATE generates 64 bits.

2. the '{} operator is not supported (I have seen a post from December mentioning this)

3. literals in the form 'b... with more than 32 bits seem not to be supported, but 64'b... works

There is a detail that is not clear to me but it is only relevant in combination with the '{} operator or with $dimensions(). According to the SystemVerilog standard (I only have 3.1a) a slice of a packed array is a packed array, for example "logic [3:0][7:0] data;" and the slice "data [1:0]". It seems ncsim has an issue here, I reported it.

What would be the easiest way for me to contribute to the Verilator test suite? Should I make a fork on GitHub, so you could fetch from it?

Regards, Iztok Jeras