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Issue #447
verilog-pretty-expr doesn't work in latest version
| Status: | Assigned | Start date: | 03/05/2012 | |
|---|---|---|---|---|
| Priority: | Normal | Due date: | ||
| Assignee: | Michael McNamara | % Done: | 0% |
|
| Category: | Indents | |||
| Target version: | - |
Description
I have verilog-auto-lineup set to 'all, but the function doesn't line anything up. It no longer prompts for my own regexp (thy myre input to the function is never used). The file I have attached doesn't lineup the assign or the localparam statements like it used to.
History
Updated by Wilson Snyder about 1 year ago
The regexp was removed about a year ago. I believe it was rev679. Please confirm if you were using a version before then. Also what regexp do you want to use? I presuming you're looking to have the assignment align but even in rev678 they didn't.
Updated by Wilson Snyder about 1 year ago
- Category set to Indents
- Status changed from New to Assigned
- Assignee set to Michael McNamara
Mac, any thoughts on this?
Updated by Wilson Snyder about 1 year ago
Email update:
"It had been a while since I've updated Verilog-mode. I had been using Rev 638 previously. So the verilog-pretty-expr function no longer lines up assign or param assigns? That's unfortunate that the feature went away. I often used the ability to use my own regexp to do alignment in my code."
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