Author Name: David Rogoff
Original Redmine Message: 818 from https://www.veripool.org

This is driving me crazy - please help!

So, I have a module I use several places in another module. I was using templates to rename the port signals with no problem:

/* my_mod AUTO_TEMPLATE "my_\([a-z]+\)_mod" (
.\(.*\)   (\1_@[]),
 ); */

my_mod
 my_happy_mod
(/*AUTOINST*/);

This works fine and appends "happy" to the signal names.

However, my next example is more complicate with a module with a couple of parameters that specify the dimensions of a 2-dimensional port. Here's the sub-module:

  #(parameter XX = 3,
     parameter YY = 4)
  (output logic [XX-1:0] [YY-1:0] port_a)

The first problem is that verilog-mode isn't dealing with this properly. Autoinst expands this to:

my_mod
 #(.XX  (PARAM_X),
    .YY  (PARAM_Y))
 my_happy_mod
(/*AUTOINST*/
 // Outputs
 .port_a (port_a_happy[PARAM_Y-1:0]),
 );

So it doesn't see the other dimension. It also defines in wrong in AUTOLOGIC.

So, since I read that there are issues with MDA support in verilog-mode, I gave it some help:

/* my_mod AUTO_TEMPLATE "my_\([a-z]+\)_mod" (
 .\(.*\)   (\1_@[]),
 .port_a   (port_a_@[PARAM_X-1:0][PARAM_Y-1:0]),

 ); */

my_mod
 #(.XX  (PARAM_X),
    .YY  (PARAM_Y))
 my_happy_mod
(/*AUTOINST*/
 // Outputs
 .port_a (port_a_happy[PARAM_X-1:0][PARAM_Y-1:0]),
 );

This, of course, instaniated correctly, and declared the signal correctly in AUTOLOGIC.

However... each instance uses different parameters, so I have to use that AUTO_TEMPLATE match in the parameter names:

/* my_mod AUTO_TEMPLATE "my_\([a-z]+\)_mod" (
 .\(.*\)   (\1_@[]),
 .port_a   (port_a_@[PARAM_X@-1:0][PARAM_Y@-1:0]),

 ); */

Which gives this:

my_mod
 #(.XX  (PARAM_X),
    .YY  (PARAM_Y))
 my_happy_mod
(/*AUTOINST*/
 // Outputs
 .port_a (port_a_happy[PARAM_Xhappy-1:0][PARAM_Yhappy-1:0]),
 );

The problem is that the parameter names have to be all upper case and the module names lower case so I got "PARAM_Yhappy" instead of "PARAM_YHAPPY" :(

So, I read the FAQ and the help page and try and use the example here:

http://www.veripool.org/wiki/verilog-mode/Faq#How-do-I-use-AUTO_TEMPLATE-to-lower-case-all-signals

``` /* my_mod AUTO_TEMPLATE "my_\([a-z]+\)_mod" ( .\(.*\) (\1_@[]), .port_a (port_a_@[PARAM_X@"(upcase @)"-1:0][PARAM_Y@"(upcase @)"-1:0]),

); */

<p>But when I expand AUTOs, I get this error:

eval: Symbol's value as variable is void: happy

<p>What am I doing wrong?  Is there a vl-xxx variable I could use instead of "@"?
<p>
<p>Thanks!!!