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Issue #45
clocks and signals not recognized in generate loops
| Status: | Closed | Start date: | 11/22/2008 | |
|---|---|---|---|---|
| Priority: | Normal | Due date: | ||
| Assignee: | Wilson Snyder | % Done: | 0% |
|
| Category: | Unsupported | |||
| Target version: | - | Estimated time: | 2.00 hours |
Description
The attached source illustrates two error messages associated with clocks and registers within generate statements:
verilator --cc tb1.v tb.cc # bussed clocks
verilator --cc tb2.v tb.cc # bussed output (work around for bussed clocks)
verilator --cc tb3.v tb.cc # work around for both busses
History
Updated by Wilson Snyder over 3 years ago
- Category set to Unsupported
- Status changed from New to Assigned
- Assignee set to Wilson Snyder
The first I'll look at supporting.
The second case isn't an error, but a warning
%Warning-MULTIDRIVEN: tb2.v:4: Signal has multiple driving blocks: count
This is a correct warning. While each bit doesn't have a different block the signal does. Verilator doesn't perform bit level analysis of this and it's not something I can work on right now, so you'll need to just turn off the warning; or simply move the initial loop outside the generate.
Updated by Wilson Snyder over 3 years ago
- File bug45.patch added
- Status changed from Assigned to Closed
- Estimated time set to 2.00
The below patch should fix this. It will be in the next release, which is fairly major, so it is likely to be a few weeks.
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