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Patch #451

Additional test of DPI used to implement generic accessor functions

Added by Jeremy Bennett about 1 year ago. Updated about 1 year ago.

Status:Closed Start date:03/08/2012
Priority:Normal Due date:
Assignee:Jeremy Bennett % Done:

0%
Category:Tests
Target version:-

Description

This test exercises the DPI interface, when used to implement generic accessor functions, as documented in the forum discussion at http://www.veripool.org/boards/3/topics/show/752-Verilator-Command-line-specification-of-public-access-to-variables.

Attached as a patch to current Git HEAD (commit a8432ed4a4ffdba5014888a11a6df74c9a608e15).

dpi_accessors.patch - Git patch for new test against HEAD (a8432ed4a4ffdba5014888a11a6df74c9a608e15) (46 kB) Jeremy Bennett, 03/08/2012 03:02 pm

dpi-accessors.patch - patch against git HEAD (commit 996f48fcf0d44d1c385ede79554cb62b71cf7c20) (31.2 kB) Jeremy Bennett, 03/27/2012 05:41 pm

History

#1
Updated by Wilson Snyder about 1 year ago

  • Category set to Tests
  • Status changed from New to Assigned
  • Assignee set to Jeremy Bennett

I tried this on other simulators and posted new fixed macros on the forum.

As I noted there they didn't allow assignments to wires, so these should be made read only:

`RW_ACCESS ([0:0], c,     {t.i_test_sub.c});
`RW_ACCESS ([7:0], d,     {t.i_test_sub.d});
`RW_ACCESS ([5:0], d_slice, {t.i_test_sub.d[6:1]});
                         t.i_test_sub.mem[32][2:0]});

Also generally I'd like to avoid "magic logfile" tests. If it's not too hard can you check the values at runtime? This makes it easier to test against other simulators, and also allows me to comment out sections of the test when debugging. (Note how many tests have a `ifdef TEST_VERBOSE around displays.)

#2
Updated by Wilson Snyder about 1 year ago

Would you like to make the updates mentioned in the last post (the read only and self testing) so I could add this to regressions?

#3
Updated by Jeremy Bennett about 1 year ago

Apologies - fell off the stack.

New version attached as diff against current git HEAD (commit 996f48fcf0d44d1c385ede79554cb62b71cf7c20). Now no longer tests for writes to wires (Verilator ought to flag this). A successful test now just prints the "All Finished" message unless run with --verbose when it also produces lots of output.

#4
Updated by Wilson Snyder about 1 year ago

  • Status changed from Assigned to Closed

Great, in git towards 3.833, thanks.

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