Verilator

Slightly modified test case from bug 456:

typedef logic signed [35-1:0] rc_t;

module test_negative( output logic o,
                      output rc_t  rc_out,
                      input       rc_t rc,
                      input logic clk);

   localparam RATIO = 2;

   rc_t rc_d[RATIO:1];

   always_ff @(posedge clk) begin
      integer  k;

      rc_d[1] <= rc;

      for( k=2; k<RATIO+1; k++ ) begin
         rc_d[k] <= rc_d[k-1];
      end
   end // always_ff @

   assign o = rc_d[RATIO] < 0;
   assign rc_out = rc_d[RATIO];

endmodule // test_negative

verilator -sv --sp --top-module test_negative test_negative.v

SC_MODULE(Vtest_negative) {
    /*AUTOATTR(verilated)*/

  public:
    /*AUTOSUBCELLS*/

    // PORTS
    // The application code writes and reads these signals to
    // propagate new values into/out from the Verilated model.
    sc_out<bool>    o;
    sc_in<bool>    clk;
    sc_out<vluint64_t>    rc_out;
    sc_in<vluint64_t>    rc;

Not clear how sign would be handled when casting signed 35-bit value to unsigned 64-bit value.