Issue #476: Support && inside sensitivity list - Verilator - Veripool

Issue #476

Status:

Feature

Start date:

04/03/2012

Priority:

Low

Due date:

Assignee:

% Done:

Category:

Unsupported

Target version:

Description

Source code:

    always @((vco_out[i_l0_ph] && is_fast_pll) or posedge areset_ipd or negedge ena_ipd or stop_vco)

Error:

%Error: ...: syntax error, unexpected &&, expecting ')'

However, the following code does compile:

    wire temp = vco_out[i_l0_ph] && is_fast_pll;
    always @(temp or posedge areset_ipd or negedge ena_ipd or stop_vco)

Subject changed from syntax error on && inside sensitivity list to Support && inside sensitivity list
Category set to Unsupported
Status changed from New to Feature

That's not synthesizable and it's also a very rare construct, so as you already noted it's low on the list.

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