Verilator

I can see how this is annoying but am not sure how to make a good general rule without disabling dangerous usages.

First, strings are just numbers in Verilog (vs SystemVerilog string). The width logic certainly could set a hidden flag when a number starts as a string, though.

This exact case is interesting, because the parameter is indeed 24 bits wide, and the right hand side can never ever match due to the WIDTH mismatch. Also consider if you set

reg [23:0] three_letters = "many_letters";

Certainly you would want a WIDTH warning in this case, since you'd only get "ers"? Perhaps equivalence could be special, but I've seen code too that uses strings for verification state names, and knowing your state is the wrong size still seems useful.

So I'd lean towards not fixing this, but am open to a counter argument.

I think in this case parameter is declared unsized and is used only for configuration, e.g.:

generate
   if( intended_device_family == "aaa" ) begin
...
   else if( intended_device_family == "aaa II" ) begin
...

If such unsized string comparisons are resolved at compile time, then I think it makes sense to suppress width warnings because the concept of width does not have meaning in such cases. And it's impossible to write code to avoid width warnings in this case.

However, I do agree that width warnings are useful in any situation where actually simulated or synthesized state is involved as in your example.

I think I've run into this before and I thought you only get width warnings when the parameter length is less than the "constant" string length. I seem to remember that sizing the parameter to the largest expected string size silenced the warnings.

parameter [255:0] intended_device_family             = "aaa";

My memory may be faulty though...