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Issue #507
assign with value containing newline fails
| Status: | Closed | Start date: | 05/07/2012 | |
|---|---|---|---|---|
| Priority: | Normal | Due date: | ||
| Assignee: | Wilson Snyder | % Done: | 0% |
|
| Category: | - | |||
| Target version: | - |
Description
Wilson,
The verilog parser would fail in case a white space is found after the 'h'
module any_logic (); 00}; // FAILS
assign AA_DATA = {8'h00}; // OKassign BB_DATA = {8'hendmodule; // any_logic
Error Message: %Error: filename.v:6: syntax error, unexpected INTEGER NUMBER, expecting ',' or '}'
regards, Walter
History
Updated by Wilson Snyder about 1 year ago
- Subject changed from assign with value containing whitespace fails to assign with value containing newline fails
- Status changed from New to Assigned
- Assignee set to Wilson Snyder
It's the newline, not the spaces.
The parser originally predated Verilog 1995 standard and so needs to see a complete verilog number with optional spaces. For now I fixed newlines, but this ideally requires rework to allow comments and such between the parts, and is related to fixing bug256.
Newline part of fix in git towards 3.316.
Updated by Wilson Snyder about 1 year ago
- Status changed from Assigned to Resolved
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