Better error when illegal bit select of array
The following code fails with an internal error:
module t (clk); input clk; wire a[0:0]; wire b[0:0]; assign b = 1'b0; assign a = b; endmodule
The error message is:
%Error: t/t_bitsel_array.v:20: Internal: Unexpected Call %Error: Internal Error: t/t_bitsel_array.v:20: ../V3AstNodes.h:585: Unexpected Call
This appears to be valid SystemVerilog. The problem doesn't occur in real code, but was discovered by accident when I mistyped
b[0:0] instead of
[0:0]b in the declaration, while investigating issue 508.
Please pull a testcase from https://github.com/jeremybennett/verilator/tree/bitsel-array.
#1 Updated by Wilson Snyder over 1 year ago
- Subject changed from Bit select of array fails to Internal error on illegal bit select of array
- Category set to Lint
- Status changed from New to Assigned
- Priority changed from Normal to Low
This code is illegal, you're using an array of wires to assign a constant. This code fails on other simulators too.
The bug will stay open as the error should obviously be better.
Committed the test as t_bitsel_wire_array_bad.pl; the test will need updating for the better error when implemented.