Verilator

The following code fails with an internal error:

module t (clk);

   input clk;

   wire  a[0:0];
   wire  b[0:0];

   assign b = 1'b0;
   assign a = b[0];

endmodule

The error message is:

%Error: t/t_bitsel_array.v:20: Internal: Unexpected Call
%Error: Internal Error: t/t_bitsel_array.v:20: ../V3AstNodes.h:585: Unexpected Call

This appears to be valid SystemVerilog. The problem doesn't occur in real code, but was discovered by accident when I mistyped b[0:0] instead of [0:0]b in the declaration, while investigating issue 508.

Please pull a testcase from https://github.com/jeremybennett/verilator/tree/bitsel-array.