signed/unsigned mixed calculation with WIDTH warning off
|Assignee:||Wilson Snyder||% Done:|
I think signed/unsigned mixed calculation is wrong.
Sample code is below.
module mod(A); output [7:0] A; wire [7:0] B; wire signed [3:0] C; assign C=-1; assign B=3; assign A=B+C; endmodule
Verilator outputs A=-2(Wrong) But NC-Verilog outputs A=18(Correct)
In this case, all number have to use unsigned.
#2 Updated by Wilson Snyder over 1 year ago
- Category set to WrongRuntimeResult
You'll note Verilator gave a WIDTH warning about this; you must have turned that warning off. When it has to width extend a signed number it lost the expansion was being done in an unsigned context. Need a big edit to fix this, so patch in a day or so.