Verilator

The following code has a loop dependency between the first two always blocks. It should execute to completion on the first positive clock edge.

module t (clk);
   input clk;
   reg      ready;

   initial begin
      ready = 1'b0;
   end

   always @(posedge ready) begin
      if ((ready === 1'b1)) begin
     $write("*-* All Finished *-*\n");
     $finish;
      end
   end

   always @(posedge ready) begin
      if ((ready === 1'b0)) begin
         ready = 1'b1 ;
      end
   end

   always @(posedge clk) begin
      ready = 1'b1;
   end
endmodule

This works fine on Icarus Verilog, but on Verilator fails to compile, with the error:

%Error: Internal Error: ../V3GraphAcyc.cpp:343: Non-cutable edge forms a loop   VERTEX=0x8bd71c0\n ALWAYS

(The example is meaningless, but was obtained by cutting down a 1100 line proprietary code where the error occurred).

Please pull the testcase from https://github.com/jeremybennett/verilator/tree/loop-crash.