Verilator

In complex designs with multiple instances of the same module, verilator generates multiple warnings for the same issue, e.g.:

%Warning-WIDTH: ...mc_channel.v:575: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'atc_req_uop_in' generates 4 bits.
%Warning-WIDTH: ...mc_channel.v:582: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'dlc_req_uop_in' generates 4 bits.
%Warning-WIDTH: ...mc_channel.v:575: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'atc_req_uop_in' generates 4 bits.
%Warning-WIDTH: ...mc_channel.v:582: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'dlc_req_uop_in' generates 4 bits.

Of course, this is not critical issue.