Parser bug in processing compiler directives in comments
Parser bug in processing compiler directive in comments. The comment should have been ignored, but it is not.
See belowe more for detail and how to reproduce (in attachment)
Script to parse Verilog and output a new Verilog with all cells prefixed with "try_"
usage: test.pl bug.v output.v
Note output.v has "bbb" unprefixed becuase of the compiler directive inside the preceding comment line is not treated correctly. If compile directive is broken (say) by inserting an extra space between ` and ifdef, the cell "bbb" is prefixed correctly. Summary: Comments are not handled correctly by the parser.
[snip] module top(); aaa();
`ifdef FIRST assign i1 = 1'b1 ; `else assign i2 = 1'b1 ; `endif // `ifdef XYZ endmodule
module aaa(); endmodule
module bbb(); endmodule
module ccc(); endmodule
#2 Updated by Wilson Snyder over 1 year ago
- Status changed from New to AskedReporter
It looks like your code is the one doing the searching for `ifndef, etc, as you're writing a raw parser that doesn't use Verilog::Preproc. If I turn on your verbose code I get
comment = // `ifdef XYZ
which is correct parsing by Verilog-Perl.
Perhaps I'm confused, if so please make very explicit as to what Verilog-Perl itself, not your script, is returning that you believe is incorrect.