Verilog-mode

I am using AUTO_TEMPLATE to use naming rules to fill in top-level connections of an module instance. But I now need the top-level naming rules to be a function of the port-direction of the instance module.

Here is a simple example to elaborate my need.

INPUT FILES:

---

module inst_module (input aaa, output wire bbb); endmodule

module top_module (); /* inst_module AUTO_TEMPLATE .\(.*\) (\1_in), .\(.*\) (\1_out), */ inst_module i_inst_module (.*); endmodule

EXPECTED RESULTS AFTER AUTO EXPANSION:

module top_module (); inst_module i_inst_module ( .aaa (aaa_in), .bbb (bbb_out) ); endmodule

THe Question is "How do I get this result using AUTO_TEMPLATE and .*