Verilog-Perl

The parser at present needs to know what is a class etc when tokens are recognized. However it's easily confused when a new symbol is declared that overrides an old symbol. For example, making a variable/function of the same name of what was a class, or vice-versa. UVM confusingly (for the users) does this all over the place. For example below foo is a class, then becomes a function.

typedef class uvm_component;
class foo extends uvm_component;
  function foo();
  endfunction
endclass

While it might be possible to further extend the lexing, this seems a bad idea. Instead the parser needs to handle the grammar ambiguities that arise from not knowing if something is a class or not until later in the parse. This means the grammar is no longer LAR but GLR. Thus the parser needs to switch to use either bison in GLR mode, or perhaps give up and go to ANTLR. ANTLR is probably better as it's a route known to work in SystemVerilog since some commercial products use it (or at least mention the ANTLR copyright, so one presumes....)

Obviously this is a great deal of work.