Missing width warning when part of a bus is compared
Verilator generates incorrect code for the comparison
~a[m:0] == 0
where the total width of "a" is larger than m. The comparison in the following example
module select_invert(input logic clk, input logic [15:0] a); always @(posedge clk) begin if ((~a[5:0] == 0) == 0) begin $write("[%0t] %%Error: t_select_invert: failed\n", $time); $stop; end end endmodule
should produce the value 1 when a is 0xffff. However, it produces the value 0.
An example in the verilator test_regress style is attached.
#2 Updated by Chandan Egbert 11 months ago
If a = 16'hffff, a[5:0] would be 6'h3f. Inverting this should give 0. comparing this with 0 should give TRUE. However I get FALSE. Looking at the generated C code, I see that the verilog expression
~a[5:0] == 0
which should evaluate to TRUE
has been translated into
(0 == (~ (0x3f & (IData)(vlTOPp->v__DOT__val))))
which evaluates to FALSE.
Am I missing something here?
#4 Updated by Wilson Snyder 11 months ago
- Subject changed from Error when part of a bus is compared to Missing width warning when part of a bus is compared
- Status changed from NoFixNeeded to Assigned
Actually there should be a WIDTH warning here to tell people what's odd.
Note also your test needs to compare only when a==40'h7fffffff as otherwise there's a time 0 race.