[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  SystemPerl
  Voneline
  WFH
General Info
  Papers

Issue #536

Regression test driver does not generate initial VCD values

Added by Jeremy Bennett 10 months ago. Updated 10 months ago.

Status:Closed Start date:07/24/2012
Priority:Normal Due date:
Assignee:Jeremy Bennett % Done:

0%

Category:Tests
Target version:-

Description

The generated main program used by regression tests includes code to generate VCD if that is configured. However it does not dump variables at t=0, so the first VCD data point is at t=10.

Please pull a one line patch to driver.pl to fix this from branch driver-vcd at:

https://github.com/jeremybennett/verilator.git

History

Updated by Wilson Snyder 10 months ago

  • Status changed from New to Closed

Thanks for the patch, committed. BTW to get the tests to pass needed to conditionality use !$self->sc_or_sp otherwise it broke SystemC tracing which calls the low level stuff each time stamp automatically.

Also available in: Atom