Verilog-mode

I'm not sure if this was intended behavior, but when AUTOINSTing an interface illegal code is generated.

Given an interface:

interface auto_intf
(  input logic          clk,
   input logic          rst_n  );

   logic                req_val;
   logic [63:0]         req_data;
   logic                req_credit;
   logic [1:0]          rsp_cmd;
   logic [63:0]         rsp_data;
   logic                rsp_credit;

endinterface

AUTOINST generates the following:

   auto_intf auto_i
     (/*AUTOINST*/
      // Interfaced
      .req_val                          (req_val),
      .req_data                         (req_data[63:0]),
      .req_credit                       (req_credit),
      .rsp_cmd                          (rsp_cmd[1:0]),
      .rsp_data                         (rsp_data[63:0]),
      .rsp_credit                       (rsp_credit),
      // Inputs
      .clk                              (clk),
      .rst_n                            (rst_n));

The signals marked as "Interfaced" are not declared as ports and cannot be connected via instantiation.

Error-[UPIMI-E] Undefined port in module instantiation
project/verif/vkits/iox/auto_module.v, 21
  Port "req_val" is not defined in interface 'auto_intf' defined in 
  "project/verif/vkits/iox/auto_intf.sv", 4
  Interface instance: auto_intf auto_i( .req_val (req_val),  .req_data 
  (req_data[63:0]),  .req_credit (req_credit),  .rsp_cmd (rsp_cmd[1:0]),  
  .rsp_data (rsp_data[63:0]),  .rsp_cre ...