Issue #541
Improper WIDTH warning on a parameterized module
| Status: | Closed | Start date: | 08/01/2012 | |
|---|---|---|---|---|
| Priority: | Normal | Due date: | ||
| Assignee: | Wilson Snyder | % Done: | 0% | |
| Category: | Lint | |||
| Target version: | - |
Description
I have five-year experience using Verilator --cc on CentOS x86_64. Thank you for this great tool.
The issue I have noticed is that Verilator 3.833 produces a WIDTH warning for a valid design containing parameterized modules.
[linux]$ cat paramtest.v
module paramtest(clk,rst,cke,idata,odata);
input clk,rst,cke;
input [7:0] idata;
output [7:0] odata;
paramtest_DFFRE#(1) dffre0(clk,rst,cke,idata[7],odata[7]);
paramtest_DFFE#(7) dffe0(clk,cke,idata[6:0],odata[6:0]);
//paramtest_DFFRE#(2) dffre0(clk,rst,cke,idata[7:6],odata[7:6]);
//paramtest_DFFE#(6) dffe0(clk,cke,idata[5:0],odata[5:0]);
endmodule
module paramtest_DFFRE(clk,rst,cke,d,q);
parameter W=1;
parameter [W-1:0] INIT={W{1'b0}};
input clk,rst,cke;
input [W-1:0] d;
output [W-1:0] q;
reg [W-1:0] q;
always @(posedge clk or posedge rst) begin
if (rst) q <= INIT;
else q <= cke ? d : q;
end
endmodule
module paramtest_DFFE(clk,cke,d,q);
parameter W=1;
input clk,cke;
input [W-1:0] d;
output [W-1:0] q;
paramtest_DFFRE#(W) dffre0(clk,1'b0,cke,d,q);
endmodule
[linux]$ export VERILATOR_ROOT=/home/honda/oss/verilator-3.831
[linux]$ $VERILATOR_ROOT/bin/verilator --lint-only paramtest.v
[linux]$ export VERILATOR_ROOT=/home/honda/oss/verilator-3.832
[linux]$ $VERILATOR_ROOT/bin/verilator --lint-only paramtest.v
[linux]$ export VERILATOR_ROOT=/home/honda/oss/verilator-3.833
[linux]$ $VERILATOR_ROOT/bin/verilator --lint-only paramtest.v
%Warning-WIDTH: paramtest.v:18: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'INIT' generates 1 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to 1 warning(s)
%Error: Command Failed /home/honda/oss/verilator-3.833/verilator_bin --lint-only paramtest.v
[linux]$ export VERILATOR_ROOT=/home/honda/oss/verilator-3.840
[linux]$ $VERILATOR_ROOT/bin/verilator --lint-only paramtest.v
%Warning-WIDTH: paramtest.v:18: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS's VARREF 'INIT' generates 1 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to 1 warning(s)
%Error: Command Failed /home/honda/oss/verilator-3.840/verilator_bin --lint-only paramtest.v
[linux]$
When I change the design from "DFFRE#(1)+DFFE#(7)" to "DFFRE#(2)+DFFE#(6)", the WIDTH warning disappears.
FYI, my installation procedure was as follows (no SYSTEMC,SYSTEMPERL).[linux]$ cd /home/honda/oss/verilator-3.8NN [linux]$ export VERILATOR_ROOT=`pwd` [linux]$ ./configure [linux]$ make [linux]$ make test_c All Tests passed
History
#1 Updated by Wilson Snyder 11 months ago
- Category set to Lint
- Status changed from New to Assigned
- Assignee set to Wilson Snyder
I believe this was broken in the fix for bug470, the top-down order of parameter module processing was violated. I have a fix but the fix breaks packages, so needs more work.
#2 Updated by Wilson Snyder 11 months ago
- Status changed from Assigned to Resolved
Fixed in git towards 3.841.
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