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Issue #543
defparam inside generate does not work correctly
| Status: | Closed | Start date: | 08/07/2012 | |
|---|---|---|---|---|
| Priority: | Normal | Due date: | ||
| Assignee: | Wilson Snyder | % Done: | 0% |
|
| Category: | TranslationError | |||
| Target version: | - |
Description
This used to work 3 months ago:
generate
if (A_FAST_SIM_MODEL)
begin
a_abstract a_inst (
...
);
defparam a_inst.PIN_WIDTH = 8;
...
end
else
begin
a_sv a_inst (
...
);
defparam a_inst.PIN_WIDTH = 8;
...
end
Now I get errors:
%Error: a.v:214: Duplicate pin connection: PIN_WIDTH %Error: a.v:130: ... Location of original pin connection
History
Updated by Alex Solomatnikov 10 months ago
Related issue: a_sv has REGULAR_WRITE_BUS_ORDERING parameter and a_abstract does not. Instantiation is correct, i.e. REGULAR_WRITE_BUS_ORDERING is specified for a_sv and not for a_abstract.
However, I get an error:
%Error: a.v:251: Pin not found: REGULAR_WRITE_BUS_ORDERING
Updated by Wilson Snyder 10 months ago
Generates were first added in Verilog 2001, the same standard which made defparam a depreciated construct. Therefore using the two together is extremely bad style, use #(...).
But as it used to work it might be a simple fix, I'll look.
Updated by Alex Solomatnikov 10 months ago
I didn't write this code - it's an IP. Unfortunately, I have to deal with it. Other simulators can handle it.
Updated by Wilson Snyder 10 months ago
- Category set to TranslationError
- Status changed from New to Resolved
- Assignee set to Wilson Snyder
Fixed in git towards 3.841.
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