Verilator

Conventionally when you trace a tristate signal the driven signal propagates up and down the hierarchy to all modules because the buses are supposed to be physically connected. This does not happen in the current implementation.

In the current implementation, the inout signal is converted to an output with the same name and an input signal with __in appended to it. So when a module drives the bus, its own signal correctly propagates up the hierarchy through the output port, but it does not properly propagate down to the children through their output ports (as expected). It does, however, propagate down the __in signal (also as expected). Wilson had talked about doing some stuff during the vcd generation to create 'Z and `X correctly, and perhaps this is the correct place to deal with this issue as well, but I think if I just switch the role and turn the original signal into the input and create an __out signal instead, then the traced signal will be more like conventional usage. This does not solve the 'Z and 'X issue, but makes the experience more traditional. The __out signal can then be dropped from the vcd dump as it contains no useful information for the trace.