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Issue #559

Nested ifdef with generate indentation bug

Added by Cyrus Cheung almost 3 years ago. Updated 6 months ago.

Status:NoFixNeededStart date:09/06/2012
Priority:NormalDue date:
Assignee:Alex Reed% Done:

0%

Category:Indents
Target version:-

Description

Hi Mac:

I've filed this bug before (a year or longer ago perhaps, though not thru veripool issue tracker) but you must be too busy to get around fixing it. Hopefully, this time it's easier for you to see the problem as I stripped the code to the minimum to show the problem. Attached file (try.v) shows that DP_CRN1V15_Connection has wrong indentation.

I did a little debugging also:

- The bug was not there in r413, but r575 on, it was there. I'm not sure which version between r413 and r575 that it got inserted. - Changing ifdef to ifndef or vice versa doesn't matter. - Get rid of the generate statements, it works - It doesn't matter if the generate keyword is inside or outside of the ifndef, same result - Having only for loop gen block or if gen block has the same effect of having multiple genblocks (nested for and if) as attached.

I appreciate you guys keep making programming verilog code simpler. Thanks a million in advance of fixing it

Thanks, Cyrus

try.v (985 Bytes) Cyrus Cheung, 09/06/2012 09:59 pm

History

#1 Updated by Alex Reed 6 months ago

  • Status changed from New to NoFixNeeded
  • Assignee set to Wilson Snyder

Indentation appears correct with latest version of verilog-mode.el - no fix required at this time. I've added a test. Wilson, please pull from https://github.com/acr4/verilog-mode/tree/issue-559

#2 Updated by Wilson Snyder 6 months ago

  • Assignee changed from Wilson Snyder to Alex Reed

Test pushed to git, thanks.

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