Verilator

Suppose you have a child module with an input and output signal. The parent only has an inout signal, and uses logic to decide when to drive the signal. If this signal is passed to the child module's input directly, the child module doesn't receive the correct input. If instead, you assign the inout to a separate wire and pass that instead, it works.

Attached patch which adds new test case and exposes the issue as well as shows the workaround.