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Internal Error: ...: ../V3Inst.cpp:294: Input pin width mismatch #595

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veripoolbot opened this issue Dec 22, 2012 · 9 comments
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Internal Error: ...: ../V3Inst.cpp:294: Input pin width mismatch #595

veripoolbot opened this issue Dec 22, 2012 · 9 comments
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area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed

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Author Name: Alex Solomatnikov
Original Redmine Issue: 595 from https://www.veripool.org
Original Date: 2012-12-22

RTL:

typedef logic [40-1:0] addr_t;
logic [$clog2($bits(addr_t))-1:0] shift,
                                  shift_ch;
flop #($clog2($bits(addr_t))) u_shift_ch_ff( .o(shift_ch), .i(shift_in-16), .* );
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-01-01T00:03:30Z

This is illegal code as an unpacked logic array cannot be connected to a logic signal.

Verilator needs better type checking on pin connections and assignment. This will probably wait until unpacked array support is fully supported as otherwise the logic will need to be redone.

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Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2013-01-03T23:53:28Z

Not sure why you are saying about unpacked array. Everything is packed in this case.

flop is defined as:

module flop #(parameter WIDTH=1)
    (
     output reg  [WIDTH-1:0] o,
     input  wire [WIDTH-1:0] i,
     input  wire clk
     );
    
    always_ff @(posedge clk)
      o <= i;

endmodule // flop

Signal declaration should be:

logic [$clog2($bits(addr_t))-1:0] shift_in,
                                   shift_ch;

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Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2013-01-04T00:05:14Z

One more thing: there is a simple workaround for this issue:

flop #($clog2($bits(addr_t))) u_shift_ch_ff( .o(shift_ch), .i(shift_in-6'd16), .* );

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-01-04T00:07:09Z

Sorry, I'm confused as to the test, please send an exact example in test_regress/t/t_EXAMPLE.v format.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-01-15T12:19:58Z

FYI this is waiting on a t_EXAMPLE.v from you, thanks.

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Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2013-01-15T20:17:12Z

Your test case is a valid case of incorrect RTL that causes internal verilator error (and I think should be addressed):

/tools/verilator/verilator-3.842/bin/verilator --cc --top-module t test_regress/t/t_inst_misarray_bad.v
%Error: test_regress/t/t_inst_misarray_bad.v:28: Internal: Unexpected Call
%Error: Internal Error: test_regress/t/t_inst_misarray_bad.v:28: ../V3AstNodes.h:645: Unexpected Call
%Error: Command Failed /tools/verilator/verilator-3.842/bin/verilator_bin --cc --top-module t test_regress/t/t_inst_misarray_bad.v

The problem I encountered is different:

/tools/verilator/verilator-3.842/bin/verilator ...
%Error: Internal Error: ...:662: ../V3Inst.cpp:294: Input pin width mismatch

I modified your test case to re-produce the issue:

module t (/*AUTOARG*/
    // Inputs
    clk
    );
    input clk;

    logic [6-1:0] foo; initial foo = 20;

    dut #(.W(6)) udut(.clk(clk),
                      .foo(foo-16));

endmodule

module dut
     #(parameter W = 1)
     (input logic clk,
      input logic [W-1:0] foo);

     genvar i;
     generate
        for (i = 0; i < W; i++) begin
           suba ua(.clk(clk), .foo(foo[i]));
        end
     endgenerate
endmodule

module suba
  (input logic clk,
    input logic foo);

    always @(posedge clk)
      $display("foo=%b", foo);

endmodule


/tools/verilator/verilator-3.842/bin/verilator --cc --top-module t t_bug595.v
%Error: Internal Error: t_bug595.v:18: ../V3Inst.cpp:294: Input pin width mismatch
%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed /tools/verilator/verilator-3.842/bin/verilator_bin --cc --top-module t t_bug595.v

If I change instantiation to this:

    dut #(.W(6)) udut(.clk(clk),
                      .foo(foo-6'd16));

then verilator completes w/o error/warning.

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Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2013-01-15T22:40:48Z

The latest version in git has the problem:

./verilator --cc --top-module t t_bug595.v
%Error: Internal Error: t_bug595.v:15: ../V3Inst.cpp:294: Input pin width mismatch
%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-01-16T00:27:03Z

Fixed in git towards 3.845.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-02-05T03:22:00Z

In 3.845.

@veripoolbot veripoolbot added area: lint Issue involves SystemVerilog lint checking resolution: fixed Closed; fixed labels Dec 22, 2019
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