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%Error: t/t_param_bit_sel.v:19: Illegal bit or array select; type does not have a bit range, or bad dimension: type is bit
It seems that Verilator assumes that a 1-bit wide parameter must be a scalar, rather than a 1-bit wide vector. Other simulators (e.g. VCS, Icarus) do not make this assumption and pass this code cleanly.
Please pull a test case from branch param-bit-sel at git@github.com:jeremybennett/verilator.git
The text was updated successfully, but these errors were encountered:
Author Name: Jeremy Bennett (@jeremybennett)
Original Redmine Issue: 603 from https://www.veripool.org
Original Date: 2013-01-16
Original Assignee: Wilson Snyder (@wsnyder)
The following code causes a Verilator error.
The error is:
It seems that Verilator assumes that a 1-bit wide parameter must be a scalar, rather than a 1-bit wide vector. Other simulators (e.g. VCS, Icarus) do not make this assumption and pass this code cleanly.
Please pull a test case from branch param-bit-sel at git@github.com:jeremybennett/verilator.git
The text was updated successfully, but these errors were encountered: