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Author Name: Jie Xu (@jiexu)
Original Redmine Issue: 607 from https://www.veripool.org
Original Date: 2013-01-22
Original Assignee: Wilson Snyder (@wsnyder)
Adding two lines to t/t_param_mem_attr.v test in verilator test_regress folder causes Verilator generating an internal fault.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [71:0] ctrl;
wire [7:0] cl; // this line is added
memory #(.words(72)) i_memory (.clk (clk));
assign ctrl = i_memory.mem[0];
assign cl = i_memory.mem[0][7:0]; // and this line
endmodule
// memory module, which is used with parameter
module memory (clk);
input clk;
parameter words = 16384, bits = 72;
reg [bits-1 :0] mem[words-1 : 0];
endmodule
However, vcs passes the same test.
This issue may relate to issue [[http://www.veripool.org/issues/583]].
The text was updated successfully, but these errors were encountered:
Author Name: Jie Xu (@jiexu)
Original Redmine Issue: 607 from https://www.veripool.org
Original Date: 2013-01-22
Original Assignee: Wilson Snyder (@wsnyder)
Adding two lines to t/t_param_mem_attr.v test in verilator test_regress folder causes Verilator generating an internal fault.
However, vcs passes the same test.
This issue may relate to issue [[http://www.veripool.org/issues/583]].
The text was updated successfully, but these errors were encountered: