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SystemVerilog 'wire logic' not supported #608

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veripoolbot opened this issue Feb 1, 2013 · 3 comments
Closed

SystemVerilog 'wire logic' not supported #608

veripoolbot opened this issue Feb 1, 2013 · 3 comments
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Ed Lander
Original Redmine Issue: 608 from https://www.veripool.org
Original Date: 2013-02-01
Original Assignee: Wilson Snyder (@wsnyder)

Hi,

We have examples of the following declarations in our code that Verilator is unhappy with:
wire logic wire_name;

This is valid SystemVerilog and both DC and Incisive seem happy with it.

NB. It should also be possible to declare a structure and infer a wire of that struct type.

Cheers,
Ed
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-02-02T14:33:12Z

All the logic was there, just needed to pull some parsing from Verilog-Perl.

Fixed in git towards 3.845.

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Original Redmine Comment
Author Name: Ed Lander
Original Date: 2013-02-04T10:05:03Z

Great, thanks Wilson.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-02-05T03:21:37Z

In 3.845.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
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