False Signal unoptimizable: circular logic warning
See attached test case showing the problem. This example shows how bit 0 of a bus is used to generate bit 1 of the same bus. Verilator is falsly detecting this as circular logic. Also shown in this test case is that this example works if the signals are not part of a bus (the `ifdef T_WORKS section).
#1 Updated by Wilson Snyder about 3 years ago
- Category changed from Lint to Unsupported
- Status changed from New to Feature
Similar UNOPTFLAT woes are also discussed in http://www.veripool.org/boards/2/topics/show/373-UNOPTFLAT-Error