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Verilator bug in handling $signed in unsigned with -Wno-WIDTH #729

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veripoolbot opened this issue Apr 3, 2014 · 8 comments
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Verilator bug in handling $signed in unsigned with -Wno-WIDTH #729

veripoolbot opened this issue Apr 3, 2014 · 8 comments
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800

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Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 729 from https://www.veripool.org
Original Date: 2014-04-03
Original Assignee: Wilson Snyder (@wsnyder)


The following module should output 0 for a = 2'b11 and b = 3'b111. But Verilator 3.856 outputs 1 instead.

module issue_002(a, b, y);
  input [1:0] a;
  input [2:0] b;
  output [0:0] y;
  assign y = $signed(a) == b;
endmodule


Analysis: The argument of $signed is self determined. So even though the comparison is a 3 bit operator, $signed(a) returns the two bit value 2'bs11. This is then extended to 3 bits, but because b is unsigned this is not a sign extension but a zero padding. Thus the expression is 3'b011 == 3'b111, which is false.

Crosscheck: Vivado 2013.4, XST 14.7, Isim 14.7 and Modelsim 10.1d implement this correctly.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-03T14:17:06Z


I'll look at this and the other one shortly, hopefully easy to fix. Would you mind posting the tests as something self-checking? (e.g. use an initial with $stop if fails, or better see "writing tests" in the documentation). Thanks.

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Original Redmine Comment
Author Name: Clifford Wolf (@cliffordwolf)
Original Date: 2014-04-03T15:21:11Z


Wilson Snyder wrote:

Would you mind posting the tests as something self-checking?

here you go: http://svn.clifford.at/handicraft/2014/verilatortest/

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-05T19:58:53Z


Thanks for the test. It correctly was making the $signed 2 bits, but the later extending due to turning off WIDTH warnings was wrong. Please note ignoring warnings makes it a lot more likely you'll hit bugs, be it in Verilator or other tools.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-05T19:59:34Z


Forgot to add pushed to git towards 3.857.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-07T02:52:15Z


The fix for this should have only addressed those logical compares which zero pad (<,>,<=,>=,==,===,! =, ! ==), but hit some additional cases as detected by #�. New fix is pending after some additional testing.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-08T01:35:19Z


New fix in git with #� working, towards 3.857.

Added a bunch of new tests, but wouldn't be surprised if there are other sign extension problems when WIDTH warnings are suppressed.

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Original Redmine Comment
Author Name: Clifford Wolf (@cliffordwolf)
Original Date: 2014-04-08T14:41:29Z


Wilson Snyder wrote:

..., but wouldn't be surprised if there are other sign extension problems when WIDTH warnings are suppressed.

Don't worry: I'm going to find and report them all. ;)

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-11T21:09:38Z


In 3.860.

@veripoolbot veripoolbot added resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800 labels Dec 22, 2019
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resolution: fixed Closed; fixed type: feature-IEEE Request to add new feature, described in IEEE 1800
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