Bug in evaluating (defined) expression with undef bits #764
Labels
area: wrong runtime result
Issue involves an incorrect runtine result from Verilated model
resolution: fixed
Closed; fixed
Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 764 from https://www.veripool.org
Original Date: 2014-05-10
Original Assignee: Wilson Snyder (@wsnyder)
This should set y=1, but verilator 6ce2a52 sets y=0 instead.
Self-contained test case:
http://svn.clifford.at/handicraft/2014/verilatortest/test013.v
http://svn.clifford.at/handicraft/2014/verilatortest/test013.cc
http://svn.clifford.at/handicraft/2014/verilatortest/test013.sh
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