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Another Verilotor bug with large shifts #774

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veripoolbot opened this issue May 24, 2014 · 2 comments
Closed

Another Verilotor bug with large shifts #774

veripoolbot opened this issue May 24, 2014 · 2 comments
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area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed

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Author Name: Clifford Wolf (@cliffordwolf)
Original Redmine Issue: 774 from https://www.veripool.org
Original Date: 2014-05-24
Original Assignee: Wilson Snyder (@wsnyder)

For a=5, b=35 this should return y=0, but Verilator f705f9b returns y=8 instead:

 module issue_051(a, b, y);
   input [3:0] a;
   input [5:0] b;
   output [3:0] y;
   assign y = 64'd0 | (a << b);
 endmodule

Self-contained test case:

http://svn.clifford.at/handicraft/2014/verilatortest/test018.v

http://svn.clifford.at/handicraft/2014/verilatortest/test018.cc

http://svn.clifford.at/handicraft/2014/verilatortest/test018.sh
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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-10T23:14:04Z

Another massively over-shifting corner case.

Fixed in git towards 3.861.

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-06-11T00:58:08Z

In 3.862.

@veripoolbot veripoolbot added area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed labels Dec 22, 2019
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area: wrong runtime result Issue involves an incorrect runtine result from Verilated model resolution: fixed Closed; fixed
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