Verilog-mode

Auto mode incorrectly deletes the comma after the a in the following verilog code:

module top
  (input [`WIDTH:0] a, /* This comma gets deleted */
   /*AUTOOUTPUT*/
   /*AUTOINPUT*/
   );

   child child(/*AUTOINST*/);

endmodule

module child(input b);
endmodule

It the preprocesser `WIDTH that causes the problem. If `WIDTH is made a constant, then the comma does not get deleted.