Inserting two symbols with same name
|Assignee:||Wilson Snyder||% Done:|
I've got a netlist from a synthesis tool, and I think it's confusing Verilator.
This is the output I'm seeing from a little test case I've put together, but it's doing the exact same thing in a larger design:
verilator -language 1364-2001 -Wno-lint --top-module intercon -sc intercon.vm -v ./sim_lib.v %Error: intercon.vm:1802: Internal Error: ../V3SymTable.h:53: Inserting two symbols with same name: v__DOT__wb4m1s2__DOT__N_15 %Error: Command Failed /home/orsoc1/Documents/julius/scratch/verilator-3.702/verilator_bin -language 1364-2001 -Wno-lint --top-module intercon -sc intercon.vm -v ./sim_lib.v make: *** [all] Error 10
The signal in question, wbm1s2.N_15, is declared as a wire, like so: wire \wb4m1s2.N_15 ;
And is used to hook up two modules inside the intercon module.
Attached is a test case.
#1 Updated by Wilson Snyder over 4 years ago
- Category set to TranslationError
- Status changed from New to Assigned
- Assignee set to Wilson Snyder
Indeed, it's because the . in the name conflicts with the internal flattened signal name. Verilator needs to consider "user's" \. different from it's own dot.
For now, please just globally eliminate the dots on the input side, in perl this would be approximately
I did that myself and it compiles ok.