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Issue #84
Possible error in precompiler macro parser
| Status: | Closed | Start date: | 05/08/2009 | |
|---|---|---|---|---|
| Priority: | Normal | Due date: | ||
| Assignee: | Wilson Snyder | % Done: | 0% |
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| Category: | - | |||
| Target version: | - | Estimated time: | 3.00 hours |
Description
Hi, I have a question regarding the precompiler macro parser.
If I'm not mistaken, Verilog-Parser doesn't support newline characters to separate formal arguments. Ex:
`define MY_MACRO ( FORMAL1, // here is a newline char, which is also a whitespace
FORMAL2 ) rest of the macro text here...Again, if I'm not mistaken I think this is valid syntax.
According to the Verilog-2005 LRM (IEEE Std 1364-2005), on section 19.3.1 (page 351 first parragraph) "The formal argument names shall be simple_identifiers, separated by commas and optionally whitespace". Focus on the optional whitespaces. Now in the same document of the formal syntax definition (Annex A), on section A.9.4 (page 509) whitespaces are defined in BNF as:
white_space ::= space | tab | newline | eofSo, if this syntax is valid, could it be included on Verilog-Perl?
Thanks, Davd
History
Updated by David A about 3 years ago
Forgot to mention, I'm using Verilog-Pearl 3.202, on Linux SLES 9
Updated by Wilson Snyder about 3 years ago
Wow, the committee botched that one. It should be the same rule as CPP, and it's definitely illegal there, but I see at least one simulator takes it so your interpretation is correct. If I were you I'd change the code and never do that again, as you're certain to hit other tools that will get this wrong.
This is somewhat a pain to fix as it reads the entire line right now, so no patch yet.
Updated by Wilson Snyder about 3 years ago
- Status changed from New to Resolved
- Estimated time set to 3.00
Fixed in the git versions of Verilog-Perl and Verilator, will be in next releases.
Updated by Wilson Snyder almost 3 years ago
- Status changed from Resolved to Closed
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