Verilog-Perl

I intentionally didn't add the newlines because it was messing up the line number count of downstream tools (that use `line).

What breaks?

Verilog-Perl isn't breaking... other scripts of my own were breaking, I think I have it under control now though.

Thanks, David

Hi Wilson,

Here is the issue I'm having: some (old) tools I'm using don't support constant functions in a localparam declaration. My RTL has that. So basically I'm using the parser to construct a hash of all localparams declared and the values (RHS of the declaration expression), and later on I'm doing inline expansion of these localparams.

Currently the parser doesn't have any callback for expression termination (when a semi-colon is found). So on the RTL I was looking for linefeeds/newlines to determine when the expression ended. This works fine given the coding conventions in our RTL of only 1 expression per line.

When I try to do the same thing with macros (macros with RTL code as the macro text) it doesn't work because the preprocessor eliminates all the newlines and I still don't have any callbacks for the expression termination.

Could you provide this callback (expression termination / semi-colon callaback) or leave an option to expand macros in multiple lines? or is there any other way you can suggest I could use to solve this problem? this would be greately appreciated.

Thanks, David

All of the Verilog::Parser callbacks should also be called when using Verilog::SigParser. So, try adding an "sub operator" callback that detects the ";".

Yes thanks.

BTW, would it be possible for the Preproc to leave newlines when the `line are suppressed (line_directives=>0)?

Thanks in advance, David