Verilog-Perl

Hello,

First of all, this is a great project and I wanted to thank you for making it free software. I've just started using it and it has been very useful. That being said I have a problem I hope you'll be able to help me with.

Currently I'm trying to implement the system task $bits (this system task resolve the number of bits needed by any bit compatible type) using the SigParse. So I need to search for type definitions and variables declarations in all dependecy tree (packages, includes, etc).

Therefore I'm using the callback "var" to identify the variables types and typedef declarations, but I have a problem when a user defined type it's declared as struct or union, I can't access the internal variable declarations of the struct or union (I can't get the field names and data types).

Is there any workaround or suggestion you could provide?

Thanks in advance